Modeling and Analysis of Non-Uniform Substrate Temperature Effects in High Performance VLSI

A non-uniform temperature profile for the chip substrate in high-performance ICs can significantly impact the performance of the global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the non-uniform temperature profiles that are encountered along the metal connections as a result of the thermal gradients in the underlying Silicon substrate. More precisely, a non-uniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal non-uniformities on signal integrity issues including speed degradation and clock skew fluctuations. Subsequently, a new thermally dependent zero-skew clock routing methodology is presented.